Electrical contact for high dielectric constant capacitors and method for fabricating the same

ABSTRACT

An electrical contact includes a non-conductive spacer surrounding conductive plug material along the full height of the contact. The spacer inhibits oxide and other diffusion through the contact. In the illustrated embodiment, the contact includes metals or metal oxides which are resistant to oxidation, and additional conductive barrier layers. The contact is particularly useful in integrated circuits which include high dielectric constant materials.

REFERENCE TO RELATED APPLICATION

The present application is a divisional of U.S. patent application Ser.No. 10/920,840, filed Aug. 18, 2004, entitled “Electrical Contact forHigh Dielectric Constant Capacitors and Method for Fabricating theSame,” which is a continuation of U.S. patent application Ser. No.10/015,811, filed Nov. 2, 2001, entitled “Electrical Contact for HighDielectric Constant Capacitors and Method for Fabricating the Same,” nowU.S. Pat. No. 6,806,187, which is a continuation of U.S. patentapplication Ser. No. 09/268,176, filed Mar. 15, 1999, entitled“Electrical Contact for High Dielectric Constant Capacitors and Methodfor Fabricating the Same,” now U.S. Pat. No. 6,348,709, and claimspriority benefit under 35 U.S.C. § 120 to the same. The presentapplication incorporates the foregoing disclosures herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to integrated circuitfabrication, and more particularly to electrical contacts to capacitors,which incorporate high dielectric constant materials.

2. Description of the Related Art

A memory cell in an integrated circuit, such as a dynamic random accessmemory (DRAM) array, typically comprises a charge storage capacitor (orcell capacitor) coupled to an access device such as a Metal OxideSemiconductor Field Effect Transistor (MOSFET). The MOSFET functions toapply or remove charge on the capacitor, thus effecting a logical statedefined by the stored charge. The amount of charge stored on thecapacitor is proportional to the capacitance C, defined by C=kk₀ A/d,where k is the dielectric constant of the capacitor dielectric, k₀ isthe vacuum permittivity, A is the electrode surface area and d is thedistance between electrodes.

The footprint allotted to memory cells is continually being reduced asintegrated circuits are scaled down in pursuit of faster processingspeeds and lower power consumption. Fabrication costs per unit of memorycan also be reduced by increasing packing density, as more cells (eachrepresenting a bit of memory) can be simultaneously fabricated on asingle wafer. As the packing density of memory cells continues toincrease, each capacitor must maintain a certain minimum charge storageto ensure reliable operation of the memory cell. It is thus increasinglyimportant that capacitors achieve a high stored charge per footprint orunit of chip area occupied.

Several techniques have recently been developed to increase the totalcharge capacity of the cell capacitor without significantly affectingthe chip area occupied by the cell. These techniques include increasingthe effective surface area A of the capacitor electrodes by creatingthree-dimensional folding structures, such as trench or stackedcapacitors.

Other techniques concentrate on the use of new dielectric materials andferroelectrics having higher permittivity or dielectric constant k. Suchmaterials include tantalum oxide (Ta₂O₅), barium strontium titanate(BST), strontium titanate (ST), barium titanate (BT), lead zirconiumtitanate (PZT), and strontium bismuth tantalate (SBT). These materialsare characterized by effective dielectric constants significantly higherthan conventional dielectrics (e.g., silicon oxides and nitrides).Whereas k=3.9 for silicon dioxide, in these materials, k can range from20-40 (Ta₂O₅) to greater than 100, with some materials having kexceeding 300 (e.g., BST). Using such materials enables the creation ofmuch smaller and simpler capacitor structures for a given stored chargerequirement, enabling the packing density dictated by future circuitdesign.

However, difficulties have been encountered in incorporating the high kmaterials into conventional fabrication flows. For example, Ta₂O₅ isdeposited by chemical vapor deposition (CVD) employing a highlyoxidizing ambient. Furthermore, after deposition, the high k materialsmust be annealed to remove carbon and/or crystallize the material. Thisanneal is also typically conducted in the presence of a highly oxidizingambient to ensure maintenance of the appropriate oxygen content in thedielectric. Depletion of oxygen would essentially leave metallic currentleakage paths through the capacitor dielectric, leading to failure ofthe cell. Both the deposition and anneal may subject surroundingmaterials to degradation. For example, polycrystalline silicon(polysilicon) plugs beneath the high k materials are subject tooxidation.

Such oxidation is not limited to immediate surrounding materials.Rather, such oxidation may diffuse directly through an insulating layer(e.g., borophosphosilicate glass or BPSG) and degrade the polysiliconcontact plug, the conductive digit/word lines, or even the siliconsubstrate itself. Oxidation of any of these structures reduces theirconductivity and is viewed as a major obstacle to incorporating high kmaterials into integrated circuits. While replacing silicon withnon-oxidizing materials prevents degradation of the plug itself, suchmaterials are expensive and many tend to allow oxygen diffusion throughthem to other oxidizable elements.

Thus, a need exists for a memory cell structure which includes asemiconductor device, an electrical contact, and a memory cellcapacitor, and which reliably integrates high dielectric constantmaterials into the process flow.

SUMMARY OF THE INVENTION

In accordance with one aspect of the invention, an electrical contact isformed between a memory cell capacitor and the silicon substrate. Theelectrical contact includes a contact plug surrounded by a siliconnitride spacer. The spacer advantageously protects the contact plug andthe silicon substrate from oxidizing environments, such as theenvironment present during subsequent processing of a high dielectriccapacitor, and from other bidirectional diffusion.

In accordance with another aspect of the invention, the contact plugcomprises CVD transition metals or CVD transition metal oxides. Thecontact plugs advantageously resist high temperatures and highlyoxidizing environments, such as the environment present duringfabrication of the high dielectric capacitor.

In accordance with yet another aspect of the invention, the electricalcontact is formed in a process, which eliminates the need for spacersalong word lines. Therefore, the extra processing steps required toproduce such digit line spacers may be avoided and contact footprint iseffectively expanded. Therefore, the electrical contact advantageouslyreduces cost and complexity of the process flow while also allowing forincreased density of memory cells.

Other aspects and advantages of the invention will be apparent from thedetailed description below and the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is described in more detail below in connectionwith the attached drawings, which are meant to illustrate and not tolimit the invention, and in which:

FIG. 1 is a schematic cross-section of a partially fabricated memorycell, in accordance with a preferred embodiment;

FIG. 2 shows the memory cell of FIG. 1 after a contact hole is etchedthrough an interlevel dielectric;

FIG. 3 shows the memory cell of FIG. 2 after deposition of a spacermaterial;

FIG. 4 shows the memory cell of FIG. 3 after a spacer etch;

FIG. 5 shows the memory cell of FIG. 4 after deposition of a conductivefiller material;

FIG. 6 shows the memory cell of FIG. 5 after an etch back or recessstep, to leave a contact plug within the contact hole;

FIG. 7 shows the memory cell of FIG. 6 after a top barrier layer hasbeen deposited;

FIG. 8 shows the memory cell of FIG. 7 after a planarization or etchback process, leaving a barrier cap for the contact plug;

FIG. 9 shows the memory cell of FIG. 8, with a memory cell capacitorformed above the contact plug;

FIG. 10 is a schematic cross-section of a partially fabricated memorycell in accordance with a second preferred embodiment, illustrating arefractive metal layer deposited over a structure similar to that ofFIG. 4;

FIG. 11 shows the memory cell of FIG. 10 after a self-align silicidationprocess;

FIG. 12 shows the memory cell of FIG. 11 after deposition of a barrierlayer and a conductive filler material;

FIG. 13 shows the memory cell of FIG. 12 after an etch back or recessstep;

FIG. 14 shows the memory cell of FIG. 13 after deposition and etch backof a barrier cap;

FIG. 15 shows the memory cell of FIG. 14 after fabrication of a memorycell capacitor over the contact plug;

FIG. 16A is a schematic cross-section of a partially fabricated memorycell in accordance with a third preferred embodiment, showing digit orword lines over a semiconductor substrate;

FIG. 16B is a top down sectional view, taken along lines 16B-16B of FIG.16A;

FIG. 17A shows the memory cell of FIG. 16A after insulating layers areformed over the word lines;

FIG. 17B is a top down sectional view, taken along lines 17B-17B of FIG.17A;

FIG. 18A shows the memory cell of FIG. 17A after contact holes areetched through the insulating layers;

FIG. 18B is a top down sectional view, taken along lines 18B-18B of FIG.18A;

FIG. 19A shows the memory cell of FIG. 18 after formation of spacers,contact plugs, and barrier layers, similar to the steps of FIGS. 3-8;

FIG. 19B is a top down sectional view, taken along lines 19B-19B of FIG.19A; and

FIG. 19C is a section taken along lines 19C-19C of FIG. 19B.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

While illustrated in the context of a contact to substrate in a memorycell, the skilled artisan will find application for the materials andprocesses disclosed herein in a wide variety of contexts. The disclosedelectrical contacts have particular utility in fabrication processflows, which include highly oxidizing environments.

FIG. 1 schematically illustrates a partially fabricated memory cell 100formed over and within a semiconductor substrate 110. While theillustrated silicon substrate 110 comprises an intrinsically dopedmonocrystalline silicon wafer, it will be understood by one of skill inthe art of semiconductor fabrication that the “substrate” in otherarrangements can comprise other forms of semiconductor layers whichinclude active or operable portions of integrated devices.

In the illustrated first preferred embodiment, a plurality of transistorgate stacks 120 each include a gate dielectric 121, a polysilicon layer122, and a conductive strap 124. The polysilicon layer 122 serves as thetransistor gate electrode, while the strap 124, typically a metal ormetal silicide, facilitates highly conductive digit or word linepropagation. Doped transistor active areas 126 are formed in thesubstrate 110 between gate stacks 120.

The gate stacks 120 are insulated from surrounding electrical elementsby sidewall spacers 130, conventionally formed by deposition and spaceretch, and protective caps 140, generally formed above the gateelectrodes 120 prior to spacer formation. The spacers 130 and caps 140preferably comprise silicon nitride. It will be understood, however,that other materials are suitable for electrically insulating the gateelectrodes from surrounding elements, and for protecting the gateelectrodes from the subsequent etching processes, as discussed withreference to FIG. 2.

Generations of integrated circuits are generally referred to by thespacing distance between the gate electrodes, also known as the criticaldimension. In the illustrated embodiments, the gate electrodes areseparated by less than about 0.40 μm. When the distance between the gateelectrodes is less than about 0.25 μm, the circuitry and processingtherefor is referred to as sub-quarter micron technology. In theillustrated embodiment, dimensions and process parameters will be givenfor quarter micron technology unless explicitly stated otherwise.Current processing technology has advanced to 0.20 μm and even 0.18 μmgate spacing. Future generations are anticipated to employ gate spacingsof 0.15 μm, 0.13 μm, 0.10 μm, etc. As described in the Backgroundsection above, as circuitry shrinks, progressively smaller real estateor footprint is allotted to each feature in the integrated circuit.

Also shown in FIG. 1 is a thick insulating layer or interleveldielectric (ILD) 150 covering the silicon substrate 110, the gateelectrodes 120, the spacers 130, and the caps 140. Typically, the ILD150 comprises a form of oxide, and is borophosphosilicate glass (BPSG)in the illustrated embodiment. Depending upon the presence or absence ofother circuit elements, the ILD 150 has a preferred thickness of about4,000 Å to 5,000 Å. For 0.15 μm technology, the ILD 150 will preferablybe about 3,000 Å to 4,000 Å.

FIG. 2 schematically illustrates the partially fabricated memory cell100 having a contact via or hole 200 etched through the ILD 150. Thecontact hole 200 can be formed by conventional photolithographictechniques and etch. The depth of the contact hole 200 is dictated bythe thickness of the ILD 150, while the width of the hole 200 ispreferably wider than the distance between gate electrodes 120. Wherethe gate spacing is about 0.25 μm, the contact hole 200 is preferablyabout 0.40 μm wide and about 4,000 Å to 5,000 Å deep. As is well knownin the art, the contact via 200 is selectively etched relative to theprotective spacers 130 and cap layer 140, such that the contact hole issaid to be self-aligned. In other words, the mask defining the hole 200need not be precisely aligned with and may be wider than the gatespacing, as shown. The caps 140 and spacers 130 are only slightly etchedby the selective chemistry, as shown

FIG. 3 schematically illustrates the partially fabricated memory cell100 having spacer material 300 deposited in the contact hole 200 andover the ILD 150. The spacer material 300 comprises an effective barrieragainst oxygen diffusion, and is preferably insulating. In theillustrated embodiment, the spacer material 300 comprises siliconnitride (SiN), desirably in a stochiometric or near-stoichiometric form(Si₃N₄). SiN is preferably deposited using a low-pressure chemical vapordeposition (LPCVD). LPCVD is preferred for conformal lining of thevertical walls of the contact hole 200, though the skilled artisan willrecognize other suitable deposition techniques.

The thickness of deposited spacer material 300 depends on the particularproperties of the spacer material 300, and upon design and operationalconsiderations. The lower limit is governed by desired barrierfunctions. For example, the spacers may need to serve as a barrieragainst diffusion of oxygen, dopants, etc. The spacer material may alsoserve to electrically isolate the gate stacks 120 from the contact to beformed. The upper limit of deposition thickness is governed by the widthof the contact hole 200. The contact hole 200 has a limit on how muchspacer material 300 can be deposited, while leaving room for conductivematerial of adequately low resistivity to function as an electricalcontact. Preferably, the illustrated silicon nitride spacer material 300has a thickness between about 30 Å and 350 Å, more preferably betweenabout 50 Å and 150 Å.

FIG. 4 schematically illustrates the partially fabricated memory cell100 after a spacer etch is conducted on the spacer material 300, formingsidewall spacers 400 along the vertical via sidewalls. As is known inthe art, a spacer etch is a directional or anisotropic etch,preferentially etching exposed horizontal surfaces. Preferably less thanabout 10% of the thickness of the vertical portions of the spacermaterial 300 is lost during this process. Most preferably, a reactiveion etch (RIE) is employed, though purely physical sputter etch is alsocontemplated.

FIG. 5 schematically illustrates the partially fabricated memory cell100 having conductive material 500 deposited into the contact hole 200and over the ILD 150, thus filling the hole 200. The conductive material500 can comprise conventional plug materials, such as CVD polysilicon ortungsten, but preferably comprises an oxidation-resistant material, suchas a transition metal or metal oxide. Suitable transition metals includeplatinum (Pt), rhodium (Rh), palladium (Pd), iridium (Ir), and ruthenium(Ru). Conductive metal oxides include iridium oxide (IrO₂) and rutheniumdioxide (RuO₂). Most preferably, the conductive material is deposited bychemical vapor deposition.

FIG. 6 schematically illustrates the partially fabricated memory cell100 after the contact plug material 500 has been etched back.Advantageously, an RIE preferentially etches horizontal surfaces andforms a recess 600, leaving a plug portion 610 of the conductive filler500 therebelow. The skilled artisan will recognize other etch backprocesses. For example, chemical-mechanical planarization or polishing(CMP) can remove horizontal surfaces and stop on the underlying ILD 150.

FIG. 7 schematically illustrates the partially fabricated memory cell100 having a conductive barrier material 700 deposited in the recess 600and over the ILD 150. In the illustrated embodiment, the barriermaterial 700 comprises titanium nitride (TiN). Alternative conductivebarriers include TiAIN and PtRh. The barrier material 700 is alsopreferably deposited using CVD techniques, although other techniques,including physical vapor deposition and spin-on deposition, may also besuitable.

FIG. 8 schematically illustrates the partially fabricated memory cell100 having the excess barrier layer material 700 removed from outsidethe recess 600, leaving a barrier cap 800 integrally formed with theplug portion 610, which together represent a completed contact plug 850.Preferably, this removal is performed by CMP. The skilled artisan willappreciate other suitable etch back techniques, including sputter etchand RIE.

The barrier cap 800 has several functions. For example, barrier cap 800prevents vertical diffusion of oxygen into the plug portion 610 duringsubsequent process flow steps, such as formation of a high dielectricused in a memory cell capacitor. Such oxidation can significantly reducethe conductivity of the contact plug 850. The barrier cap 800 alsoprevents dopant diffusion, including out diffusion of electrical dopants(e.g., boron, arsenic or phosphorus) from the active area 126.

The embodiment of FIGS. 1-8 thus provides an electrical contact 850having an insulating spacer 400 surrounding the sidewalls of the contactplug 850. The spacer 400 protects the contact plug 850 from oxidationduring subsequent process flows, for example, from the highly oxidizingenvironments associated with the formation of high dielectric constantcapacitors in memory cells. Such highly oxidizing environments couldotherwise oxidize plugs of conventional construction, rendering themnon-conductive. Moreover, even with state-of the-art transition metal ormetal oxide plugs, as utilized in the preferred embodiment, highly richoxygen environments and high thermal energy during high k materialformation (including curing anneal) can lead to oxygen diffusion throughthe ILD 150 to sidewalls of the plug 850. The illustrated spacers 400prevent such diffusion from continuing through the plug 850 and into theactive area 126.

FIG. 9 illustrates an exemplary memory cell capacitor 900 formed overthe plug 850. The memory cell capacitor 900 includes a bottom or storageelectrode 910, a capacitor dielectric 920, and a top or referenceelectrode 930. An insulating layer 940 preferably surrounds and providesa container-shaped template for the bottom electrode 910. As discussedabove, the dielectric 920 preferably comprises a material having a highdielectric constant, i.e., greater than about 10, so as to enablesmaller and simpler memory cell capacitor structures. Such materialsinclude tantalum oxide (Ta₂O₅), barium strontium titanate (BST),strontium titanate (ST), barium titanate (BT), lead zirconium titanate(PZT), and strontium bismuth tantalate (SBT). These materials arecharacterized by effective dielectric constants significantly higherthan conventional dielectrics (e.g., silicon oxides and nitrides).Whereas k equals 3.9 for silicon dioxide, the dielectric constants ofthese new materials can range from 20 to 40 (tantalum oxide) to greaterthan 100 (e.g., BST, for which k $ 300), and some even higher (600 to800).

An exemplary dielectric 920 comprises SBT, deposited by chemical vapordeposition or spin-on deposition, followed by a curing anneal tocrystallize the dielectric. The anneal is preferably performed betweenabout 450 EC and 950 EC. This crystallization of a complex oxide such asSBT should be performed in an oxygen ambient, preferably an O₂, O₃, N₂O,NO, or other oxygen-containing ambient. During this high temperatureoxidation step, oxygen tends to diffuse outward from the dielectriclayer 920.

The structure and material for the illustrated memory cell capacitor 900are merely exemplary. The skilled artisan will readily appreciate theutility of the illustrated contact structure in a variety of integratedcircuit designs.

FIGS. 10-15 illustrate a partially fabricated memory cell 1000 is inaccordance with a second preferred embodiment. Similar features to thoseof the previous embodiment will be referenced by like numerals, forconvenience. With reference initially to FIG. 10, the memory cell 1000has been fabricated by process steps similar to those described withrespect to FIGS. 1-4, such that sidewall spacers 400 are formed incontact hole 200, as shown. In addition to the non-conductive barrier,properties of the sidewall spacers 400, the memory cell 1000 of thesecond embodiment includes conductive liners for superior barrierproperties and improved conductivity.

In particular, a metal layer 1010, preferably a refractory metal such astitanium, tungsten, titanium nitride, tungsten nitride, etc., isdeposited into the contact hole 200 and over the ILD 150. The thicknessof the metal layer 1010 depends on the geometry of the circuit design,and operational considerations. An upper limit on the thickness of themetal layer 1010 is influenced by a desire to avoid overconsumption ofthe active area 126 during subsequent annealing, as will be clear fromthe disclosure below. The metal layer 1010 should be thick enough,however, to react with silicon and produce a silicide layer which issufficient to consume any native oxide on the surface of the substrate110, and to provide good adhesive contact with a subsequently depositedlayer. Additionally, the metal layer 1010 should be deposited in anappropriate thickness to cover the active area 126 at the bottom of thedeep contact hole 200. Preferably, the metal layer 1010 comprisestitanium with a thickness between about 25 Å and 150 Å.

With reference to FIG. 11, the substrate is then annealed to react themetal layer 1010 with the substrate 110, forming a silicide cladding1100 over the active area 126. As the silicide cladding 1100 forms onlywhere the metal layer 1010 contacts silicon, this process is referred toin the art as a self-aligned silicide, or salicide process. Thesilicidation reaction consumes any native oxide at the surface. Thisfunction is particularly advantageous where the filler metals, such asnoble and other transition metals, do not readily react with the siliconof the preferred substrate 110. Unreacted metal is then selectivelyetched, typically with a selective wet etch, such that only the silicidecladding 1100 remains. This silicide cladding 1100 forms electricalcontact between the active area 126 and a later-deposited layer.

FIG. 12 illustrates the partially fabricated memory cell 1000 after aconductive barrier liner 1200 has been deposited into the contact hole200 and over the ILD 150, followed by the conductive plug material orfiller 500. The conductive barrier liner 1200 preferably comprises anon-oxidizing, dense, small grain material, such as metal nitrides,metal silicides, etc., which demonstrate good barrier properties.Titanium nitride (TiN), for example, can be conformally deposited bymetal organic or inorganic CVD. Another preferred material comprisesTiAIN.

The conductive barrier liner 1200 is desirably thin enough to leave roomfor the more highly conductive filler 500, and thick enough to serve asa barrier. The preferred thickness is between about 25 Å and 300 Å for a0.40 μm contact hole. The conductive barrier liner 1200 advantageouslyinhibits silicon, oxygen and dopant.diffusion.

As in the previous embodiment, the filler 500 is then deposited into thecontact hole 200 and over the conductive barrier layer 1200. The filler500 can be as described with respect to FIG. 5.

With reference to FIGS. 13 to 15, the illustrated embodiment includessubsequent steps similar to those described above with respect to FIGS.6 to 9. In particular, the filler 500 is recessed (FIG. 13), aconductive barrier deposited and etched back to leave a barrier cap 800(FIG. 14), and a memory cell capacitor 900 formed over the contact plug850 (FIG. 15). Advantageously, the capacitor 900 incorporates a highdielectric constant material 920. During the recess step, shown in FIG.13, both the filler 500 and the conductive barrier liner 1200 arepreferably recessed, and the barrier cap 800 completes the conductivebarrier on all sides of the plug portion 610. Alternatively, the linercan be first deposited and etched back, and the filler depositedthereafter. In this case, only the filler needs to be recessed, suchthat the liner extends around the barrier cap.

Thus, the second embodiment provides the contact plug 850 which includesconductive barriers 800, 1100, and 1200 on all sides (top, bottom andsidewalls), as well as the non-conductive barrier, or sidewall spacers400 around the contact sidewall and extending the depth of the plugportion 610 (thereby covering the major surface of the plug portion 610.The contact plug 850 thus provides electrical contact between thesubstrate 110 and the overlying cell capacitor 900, while at the sametime blocking potential diffusion paths to or from the substrate 110.

FIGS. 16A-19C illustrate a process flow in accordance with a thirdpreferred embodiment. In particular, FIG. 16A illustrates a partiallyfabricated memory cell 1600 including a semiconductor substrate 1610 andtransistor gate stacks 1620 formed thereover on either side of atransistor active area 1626. As with the previously describedembodiments, the substrate 110 preferably comprises a dopedmonocyrstalline silicon wafer and the gate stacks 1620 each preferablycomprise a gate dielectric 1621, a polysilicon electrode layer 1622, ametal strap 1624 and protective cap 1640. Notably, the gate stacks 1620do not include sidewall spacers.

FIG. 16B illustrates a top view of the gate stacks 1620 of FIG. 16A. Asshown, the stacks 1620 extend laterally across the substrate, serving asdigit or word lines between transistors. While not shown, it will beunderstood that field isolation elements are typically also formedwithin the substrate, to isolate transistors from one another.

FIG. 17A illustrates the cell 1600 after a first insulating layer 1700and a second insulating layer or ILD 1750 are deposited over the gatestacks 1620 and the silicon substrate 1610. The first insulating layer1700 prevents direct contact between the overlying second insulatinglayer or ILD 1750, preferably comprising BPSG, and the gate stacks 1620.Accordingly, the first insulating layer 1700 desirably inhibits dopantdiffusion from the overlying BPSG into the gate stacks 1620 and thesubstrate 1610. In the illustrated embodiment, the first insulatinglayer 1700 comprises oxide deposited from tetraethylorthosilicate,conventionally referred to as TEOS. As is known in the art, TEOS can bedeposited by plasma CVD with excellent step coverage. The thickness forthe first insulating layer 1700 is preferably less than about 500 Å,more preferably between about 200 Å and 300 Å, while the secondinsulating layer 1750 is preferably about 3,000 Å to 4,000 Å thick.

FIG. 17B is a sectional top down view of the cell 1600. The broken linesindicate that the gate stacks 1620 are hidden below the insulatinglayers 1750,1700.

Though not illustrated, the insulating layers can optionally beplanarized down to the level of the gate stacks at this point. CMP wouldabrade the ILD and the first insulating layer until the nitride caps ofthe gate stacks are exposed. Such a process would advantageously lowerthe height of the contact to be formed, for a given contact width, thusfacilitating easier fill and further scaling of the integrated circuitdesign.

FIGS. 18A and 18B schematically illustrate the partially fabricatedmemory cell 1600 having a via or contact hole 2000 etched through theinsulating layers 1750, 1700 to expose the underlying transistor activearea 1626. FIG. 18B is a top down section of the partially fabricatedmemory cell 1600 of FIG. 18A, showing two such contact holes 2000adjacent one another. Preferably, the contact holes 2000 are etched byphotolithography and selective etch. The etch chemistry is selected toconsume oxide without attacking the nitride cap or conductive layers ofthe gate stacks 1620. As in the previous embodiments, the depth of eachcontact hole 2000 is determined by the thickness of the insulatinglayers 1700, 1750, the gate spacing is preferably less than about 0.40μm, and the contact hole width is preferably greater than the gatespacing. For example, if the gate spacing is about 0.25 μm, the contacthole 2000 is preferably about 0.4 μm wide and about 4,000 Å to 5,000 Ådeep (assuming the BPSG has not be planarized down to the level of thegate stacks).

As shown, the TEOS of the illustrated first insulating layer 1700 andthe nitride caps 1640 will typically be laterally recessed somewhat inthe course of the etch. The conductive layers of the gate stack 1620,however, are largely undamaged by the etch.

FIGS. 19A-19C illustrate exemplary contact plugs 2850 of the thirdpreferred embodiment. As illustrated, each plug 2850 includes anon-conductive spacer 2400, preferably comprising silicon nitride, and aconductive filler material 2610, preferably comprising a non-oxidizingmetal or metal oxide. Additionally, a conductive barrier cap 2800 isformed over the recessed filler material 2610. The illustrated contact2850 thus resembles the contact 850 of FIGS. 3-9, and the processes fortransforming the cell 1600 from the structure of FIG. 18A to that ofFIG. 19A can be as described with respect to FIGS. 3-9.

Unlike the first embodiment, however, the spacers 2400 of the firstembodiment are in direct contact with the conductive layers 1622, 1624of the gate stack 1620, without any intervening gate sidewall spacers.Rather than the gate spacers, only the non-conductive spacers 2400lining the contact hole 2000 (or surrounding the contact plug 2850)electrically insulate the contact plug 2850 from the gate stacks 1620.This electrical insulation is provided only at the contacts. In areasbetween transistors, where the gate stack 1620 functions only as a wordline, the gates are insulated only by the first and second insulatinglayers 1700, 1750.

Thus, only one insulating layer is provided between the conductive gatestacks 1620 and each contact 2850. In contrast, FIG. 9 shows both thegate spacer 130 and the contact spacer 400 interposed between theelectrode layers 122, 124 and the contact 850. Thus, the usable spacebetween the gate stacks 1620 is widened, relative to the process flowsof the previously discussed embodiments. Omission of the gate spacersleaves more space for conductive contact material, and facilitatesfurther scaling.

Although the foregoing invention has been described in terms of certainpreferred embodiments, other embodiments will be apparent to those ofordinary skill in the art. For example, a process flow similar to thatof the second embodiment (FIGS. 10-15) can be substituted into the thirdembodiment, thereby including a silicide cladding at the active areasurface and a conductive liner. Additionally, other combinations,omissions, substitutions and modification will be apparent to theskilled artisan, in view of the disclosure herein. Accordingly, thepresent invention is not intended to be limited by the recitation of thepreferred embodiments, but is instead to be defined by reference to theappended claims.

1. A method of reducing corrosion of a conductive plug in an electronicdevice, the method comprising: forming a first substantially verticalbarrier layer in an interlevel dielectric, wherein the first barrierlayer comprises an insulative material; forming a second substantiallyvertical barrier layer within the first barrier layer, wherein thesecond barrier layer comprises a conductive material; forming asubstantially vertical electrical contact between an upper semiconductordevice and a lower semiconductor device, wherein forming the electricalcontact includes forming a conductive plug within the first barrierlayer thereby double wrapping the conductive plug from at least theinterlevel dielectric using at least the first and second barrierlayers; and forming the upper semiconductor device.
 2. The method claim1, wherein the forming the electrical contact further comprises formingan upper barrier layer between the conductive plug and the uppersemiconductor device.
 3. The method claim 1, wherein the first andsecond barrier layers form a double barrier against corrosion of theelectrical contact during at least the formation of at least a portionof the upper semiconductor device.
 4. The method of claim 1, wherein theinsulative material comprises silicon nitride.
 5. The method of claim 1,wherein the upper semiconductor device comprises a capacitorincorporating a high dielectric constant material.
 6. A process forforming an electrical interconnection between a capacitor and an activearea in a semiconductor, comprising: providing an interlevel dielectricover said semiconductor; etching said interlevel dielectric to form acontact hole exposing the active area; depositing a non-conductive layerinto said contact hole; conducting a spacer etch on said non-conductivelayer to define a non-conductive liner and expose said active area insaid contact hole; depositing a conductive material within saidnon-conductive liner in said contact hole to form a contact plug; andforming a capacitor over said contact plug.
 7. The process of claim 6,wherein said conductive material comprises a non-oxidizing conductor. 8.The process of claim 7, wherein said conductor is selected from thegroup consisting of platinum, rhodium, palladium, iridium, ruthenium,rhodium oxide, iridium oxide ruthenium dioxide, and combinationsthereof.
 9. The process of claim 7, further comprising forming asilicide between said conductive material and said active area.
 10. Theprocess of claim 9, wherein forming said silicide comprises: depositinga titanium layer within said non-conductive liner in said contact hole;and reacting said titanium layer with said substrate.
 11. The process ofclaim 9, further comprising depositing a conductive barrier layer intothe contact hole over the silicide.
 12. The process of claim 11, whereinsaid conductive barrier layer comprises a metal nitride.
 13. The processof claim 6, wherein conducting a spacer etch on said non-conductivelayer comprises selectively etching the interlevel dielectric relativeto a protective insulator over an adjacent transistor gate.
 14. Theprocess of claim 6, wherein said capacitor incorporates a highdielectric constant material.
 15. The process of claim 14, whereinforming the capacitor includes annealing the high dielectric constantmaterial in an oxidizing atmosphere.
 16. A method of forming a contactin an integrated circuit, the method comprising: etching a contact viathrough an interlevel dielectric; lining the contact via with aninsulating liner; lining the insulating liner with a conductive liner;and filling the contact via with a conductive material.
 17. The methodof claim 16, wherein filling the contact via comprises depositing atransition metal.
 18. The method of claim 16, wherein filling thecontact via comprises depositing a conductive oxide.
 19. A semiconductordevice capable of reducing corrosion of a conductive plug, thesemiconductor device comprising: a first barrier liner in an interleveldielectric, wherein the first barrier liner comprises an insulativematerial; a second barrier liner within the first barrier liner, whereinthe second barrier liner comprises a conductive material; an uppersemiconductor device; a lower semiconductor device; and an electricalcontact between the upper semiconductor device and the lowersemiconductor device, wherein the electrical contact includes aconductive plug within the first barrier liner, the conductive plugbeing double wrapped from at least the interlevel dielectric by at leastthe first and second barrier liners.
 20. The semiconductor device ofclaim 19, wherein the electrical contact further comprises a thirdbarrier cap between the upper semiconductor device and the conductiveplug.